1. Field of the Invention
The present invention relates to an image processing device for use in, e.g., a digital still camera, a facsimile machine, a digital copy machine, a videophone, a video CD player, a DVD player, etc. Specifically, the present invention relates to an image processing device which achieves an increase in the processing speed of pipeline image processing performed between discrete cosine transform processing/inverse discrete cosine transform processing and Huffman-encoding processing/Huffman-decoding processing for compression/expansion of color images; accurate encoding/decoding; and a decrease in circuitry size.
In the description hereinbelow, a discrete cosine transform is referred to as xe2x80x9cDCTxe2x80x9d, and an inverse discrete cosine transform is referred to as an xe2x80x9cinverse DCTxe2x80x9d.
2. Description of the Related Art
There are standards for high efficiency image encoding processing (data compression processing for image information) provided by a plurality of organizations, whereby compatibility of compressed data among various applicable fields is secured. For example, in the field of electronic communications, there is the H. 261 standard (which is a CCITT recommendation). Furthermore, in the field of recording technology, the International Standards Organization (ISO) standardize an MPEG as dynamic image encoding processing and a JPEG as still image encoding processing.
In encoding processing based on such standards, as shown in FIG. 10, encoding processing for dynamic images is achieved by a combination of a plurality of unit processing algorithms.
In the standardized dynamic image encoding processing as shown in FIG. 10, captured image information is converted into an electric signal by a charge coupled device (CCD) 1, and the electric signal is digitally converted by an A/D converter 2. The digitally converted image data is supplied to a motion estimation processing section 3. The motion estimation processing section 3 compares the image data from the A/D converter 2 with data output from a frame memory 12 in which preceding frame images are accumulatively stored to determine an optimum one of the preceding frame images in the frame memory 12. Output data from the motion estimation processing section 3 is subjected to a frame differential process 4, and supplied to a DCT processing section 5.
The DCT processing section 5 divides an image corresponding to the supplied image data into blocks each having a particular size, and DCT processes the image data on a block-by-block basis. In a quantization processing section 6, the DCT-processed image data is quantized according to a quantization factor into image data components. The image data components are compressed by Huffman-encoding processing in a Huffman-encoding processing section 7. The compressed image data components are recorded in a recording section 8.
On the other hand, in an inverse quantization processing section 9, the image data components obtained in the quantization processing section 6 are inversively quantized according to the above quantization factor into image data. The inversively quantized image data is output to an inverse DCT processing section 10. The inverse DCT processing section 10 inversively DCT-processes the inversively quantized image data on the block-by-block basis. The inversively DCT-processed image data is subjected to addition processing with the optimum one of the proceeding frame images which has been determined by the motion estimation processing section 3, and is accumulated in a frame memory 12. Frame image data in the frame memory 12 is fed back to the motion estimation processing section 3 for subsequent motion estimation processing.
Furthermore, standardized encoding/decoding processing for still images is achieved by a combination of a plurality of unit processing algorithms as shown in FIG. 11.
In the standardized encoding/decoding processing for still images shown in FIG. 11, captured image information is converted by a CCD 1 into an electric signal, and the electric signal is digitally converted by an A/D converter 2. The image data digitally converted by the A/D converter 2 is output to a DCT processing section 5. The DCT processing section 5 divides an image of the image data into a plurality of blocks each having a particular size, and DCT-processes the image data on block-by-block basis.
In a quantization processing section 6, the image data which has been DCT-processed in the DCT processing section 5 is quantized according to a quantization factor into image data components. The image data components are compressed by Huffman-encoding processing in a Huffman-encoding processing section 7. The compressed image data components obtained in the Huffman-encoding processing section 7 are recorded in a recording section 8.
On the other hand, in the case where the compressed image data components recorded in the recording section 8 are decompressed to reproduce the original captured image, the compressed image data components are read out from the recording section 8 and decoded in a Huffman-decoding processing section 13, whereby the compressed data components are converted into image data components. These image data components are inversively quantized by an inverse quantization processing section 9, whereby the image data components are converted into image data. This image data is output to an inverse DCT processing section 10. The inverse DCT processing section 10 inversively DCT-processes the image data on the block-by-block basis, thereby reproducing an image which is substantially the same as the original captured image.
In the encoding process for dynamic images shown in FIG. 10, in almost all the processing performed in the motion estimation processing section 3 and the downstream sections thereof, an entire image is divided into a mesh-like matrix formed by a plurality of image regions, and each type of processing is performed on each image region. Also in the encoding/decoding process for still images shown in FIG. 11, in almost all the processing performed in the DCT processing section 5 and the downstream sections thereof, an entire image is divided into a mesh-like matrix formed by a plurality of image regions, and each type of processing is performed on each image region. There are two types of image region-based processing; an image is processed on the units of a region formed by 8xc3x978 pixels (a block) (e.g., processing in the DCT processing section 5); or an image is processed on the units of a region formed by 16xc3x9716 pixels (a macroblock) (e.g., a processing in the motion estimation processing section 3). Hereinbelow, processing on the units of an 8xc3x978 pixel region (on the block-by-block basis) is described in detail.
In the encoding process, image data is sequentially input to the DCT processing section 5 on the block-by-block basis (i.e., on the units of an 8xc3x978 pixel region). In the DCT processing section 5, DCT processing is performed on the image data (two-dimensional image information) on the block-by-block basis (i.e., on the units of an 8xc3x978 pixel region). This two-dimensional DCT processing is performed by executing one-dimensional DCT processing in a horizontal (row) direction and one-dimensional DCT processing in a vertical (column) direction. The two-dimensional DCT processing on the units of an 8xc3x978 pixel region is represented by following arithmetic expression (1):
F(U,V)=(xc2xc)C(U)C(V)xcexa3xcexa3f(i,j)cos[(2i+1)Uxcfx80/16]cos[(2j+1)Vxcfx80/16]xe2x80x83xe2x80x83(1) 
where f(i,j) is pixel data, and the initial value for i and j is 0. In expression (1),
when U=0, C(U)=1/2;
when Uxe2x89xa00, C(U)=1;
when V=0, C(V)=1/2; and
when Vxe2x89xa00, C(V)=1.
Data Fuv which has been obtained after the two-dimensional DCT processing is output to the quantization processing section 6. The quantization processing section 6 quantizes the two-dimensional DCT processed data Fuv according to a quantization factor Quv as shown by expression (2):
Suv=Fuv/Quvxe2x80x83xe2x80x83(2) 
where Suv denotes an image data component obtained after quantization processing.
As described above, in the two-dimensional DCT processing in the DCT processing section 5, the one-dimensional DCT processing according to the column direction order is performed after the one-dimensional DCT processing according to the row direction order. Then, the results of the one-dimensional DCT processing according to the column direction order, i.e., data Fuv, are sequentially supplied according to the row direction order to the quantization processing section 6 for conversion into an image data component Suv. Thus, in the quantization processing section 6, quantization processing is performed for the two-dimensional image data from the DCT processing section 5 on the units of a block formed by 8xc3x978 pixels according to the column direction order. The column direction order is shown in FIG. 12.
The image data components obtained after the quantization processing in the quantization processing section 6 are output to the Huffman-encoding processing section 7 according to the column direction order shown in FIG. 12. In the Huffman-encoding processing section 7, the order of the Huffman-encoding processing is a zigzag-scan order or an alternate-scan order. Therefore, data output from the quantization processing section 6 should be converted so as to comply with the zigzag-scan order or the alternate-scan order. The zigzag-scan order is shown in FIG. 13, and the alternate-scan order is shown in FIG. 14. The image data which has been compressed by the Huffman-encoding processing is recorded in the recording section 8.
On the other hand, in the case where the compressed image data recorded in the recording section 8 is decompressed to reproduce the original captured image, the compressed image data is read out from the recording section 8 and decoded in a Huffman-decoding processing section 13, whereby the compressed image data is converted into image data component Suv. The image data component obtained by the Huffman-decoding processing is output according to the zigzag-scan order or the alternate-scan order. The image data component Suv output from the Huffman-decoding processing section 13 is inversively quantized according to a quantization factor Quv in the inverse quantization processing section 9 as shown by expression (3):
Fuv=Quvxc3x97Suvxe2x80x83xe2x80x83(3) 
where Fuv represents an inversively quantized image data component.
The image data from the inverse quantization processing section 9 is sequentially input to the inverse DCT processing section 10 on the block-by-block basis (i.e., on the units of an 8xc3x978 pixel region). In the inverse DCT processing section 10, inverse DCT processing is performed on each block (8xc3x978 pixel region) of the two-dimensional image data. This two-dimensional inverse DCT processing is performed by executing one-dimensional inverse DCT processing in a horizontal (row) direction and one-dimensional inverse DCT processing in a vertical (column) direction. The two-dimensional DCT processing performed on an 8xc3x978 pixel region is represented by following arithmetic expression (4):
f(i,j) (xc2xc)xcexa3xcexa3C(x)C(y)F(x,y)cos[(2i+1)xxcfx80/16]cos[(2j+1)yxcfx80/16]xe2x80x83xe2x80x83(4) 
where F(x,y) is pixel data, and the initial value for x and y is 0. In expression (4),
when x=0, C(x)=1/2;
when xxe2x89xa00, C(x)=1;
when y=0, C(y)=1/2; and
when yxe2x89xa00, C(y)=1.
In the processing for the two-dimensional image data on the block-by-block basis (i.e., on the units of an 8xc3x978 pixel region) in the inverse quantization processing section 9, each block is processed in the same processing order as that of the one-dimensional inverse DCT processing in the vertical (column) direction of image data in the inverse DCT processing section 10 as shown in FIG. 12.
As seen from the above, the data output order from the quantization processing section 6 and the data input order in the inverse quantization processing section 9 are as shown in FIG. 12; on the other hand, the data input order in the Huffman-encoding processing section 7 and the data output order from the Huffman-decoding processing section 13 are the zigzag-scan order (FIG. 13) or the alternate-scan order (FIG. 14). Accordingly, a buffer memory for a primary memory is required for pipeline processing between the quantization processing section 6 and the Huffman-encoding processing section 7, and between the Huffman-decoding processing section 13 and the inverse quantization processing section 9. Therefore, it is difficult to increase the speed of the pipeline processing, and to correctly perform encoding/decoding processing because the buffer memory is used for the primary memory. Moreover, it is difficult to reduce the size of the circuitry.
Methods for increasing the speed of pipeline processing are disclosed in, for example, Japanese Laid-Open Publication No. 3-76398 and Japanese Laid-Open Publication No. 10-334225.
Now, a method disclosed in Japanese Laid-Open Publication No. 3-76398 is described. In the case where the encoding is performed according to this method, as shown in a block diagram of FIG. 15 and in a timing chart of FIG. 16, at time T1 when all the processing for image data in a DCT processing section 101 and a quantization processing section 102 are completed, writing the processing results from the quantization processing section 102 into a FIFO memory 103 is begun. At the same time, reading data from the FIFO memory 103 and inputting the data into a Huffman-encoding processing section 104 is begun. Then, at time T2 when the writing of the processing results from the quantization processing section 102 into the FIFO memory 103 is completed, next image data is input to the DCT processing section 101 to start DCT processing thereof.
Furthermore, in the case where decoding is performed, as shown in a block diagram of FIG. 17 and in a timing chart of FIG. 18, at time T3 when all processing for the compressed image data input to a Huffman-decoding processing section 108 is completed, writing the processing results from the Huffman-decoding processing section 108 into a FIFO memory 107 is begun. At the same time, reading data from the FIFO memory 107 and inputting the data into an inverse quantization processing section 106 and an inverse DCT processing section 105 is begun. Then, at time T4 when writing the processing results from the Huffman-decoding processing section 108 into the FIFO memory 107 is completed, next compressed image data is input to the Huffman-decoding processing section 108 to start Huffman-decoding processing thereof.
According to a method disclosed in Japanese Laid-Open Publication No. 10-334225, as shown in a block diagram of FIG. 19 and in a timing chart of FIG. 20, a plurality of processings are assigned to a plurality of stages, i.e., a processing stage (i) 202 and a processing stage (i+1) 204. For that purpose, a double buffer is provided between the processing stages 202 and 204. The double buffer is formed by two buffers 203aand 203b each having a size capable of storing the processing result of the respective processing stages. These buffers 203a and 203b are controlled by local control devices 216 and 217 and a general control device 218.
In particular, the general control device 218 controls the switching between the buffers 203a and 203band the start of processing at the respective processing stages 202 and 204 by: an LSTART signal according to the predetermined longest processing time at each of the processing stages; an EMPTY signal which indicates the presence of input data in an input buffer 201; and a FULL signal which indicates the presence of output data in an output buffer 205. Once the local control devices 216 and 217 are commanded by the LSTART signal from the general control device 218 to start processing, the local control devices 216 and 217 are operated separately from each other and from the general control device 218 during a processing time of a processing stage which consumes the predetermined longest processing time amongst the processing stages. In this way, double control by the local control devices 216 and 217 and the general control device 218 deconcentrates the load imposed on the control devices.
More specifically, at time T5, the processing at the processing stage (i) 202 is begun, and then its processing result R(1) is written into the buffer 203a. At time T6 when the processing at the processing stage (i) 202 is completed, the processing at the subsequent processing stage (i+1) 204 is begun, and then its processing result R(2) is written into the buffer 203b. Moreover, at a predetermined time during the processing at the subsequent processing stage (i+1) 204, the processing result R(1) is read out from the buffer 203a. By repeating this procedure, processing at a processing stage which consumes the longest processing time amongst the processing stages 202 and 204 can be executed without interrupted or stopped.
According to the method disclosed in Japanese Laid-Open Publication No. 3-76398, the DCT processing and the quantization processing are performed in parallel with the Huffman-encoding processing. Moreover, the Huffman-decoding processing is performed in parallel with the inverse quantization process and the inverse DCT processing.
However, in the encoding process, during the writing of data into the FIFO memory 103 (T2-T1: see FIG. 16), the DCT processing, the quantization processing, and the Huffman-encoding processing are stopped. That is, high speed processing is not appropriately achieved. Similarly, in the decoding process, during the writing of data into the FIFO memory 107 (T4-T3: see FIG. 18), the inverse quantization processing and the inverse DCT processing are stopped. That is, high speed processing is not appropriately achieved.
Furthermore, in the encoding process, at time Ti when all the processing for the image data input to the DCT processing section 101 and to the quantization processing section 102 is completed, writing the processing results from the DCT processing section 101 and the quantization processing section 102 in the FIFO memory 103 is begun, and at the same time, reading data from the FIFO memory 103 and inputting the data into the Huffman-encoding processing section 104 is begun. However, in this method, when the write cycle and the read cycle are equal, the address for writing according to the column direction order overtakes the address for reading according to the zigzag-scan order or the alternate-scan order. In such a case, it is impossible to read all of the DCT processing results which have been written into the memory 103 according to the column direction order. Thus, accurate encoding processing cannot be performed.
Similarly, in the decoding process, at time T3 when all the processing for compressed image data input to the Huffman-decoding processing section 108 is completed, writing the processing results from the Huffman-decoding processing section 108 into the FIFO memory 107 is begun, and at the same time, reading data from the FIFO memory 107 is begun. Accordingly, when the write cycle and the read cycle are equal, the address for writing according to the zigzag-scan order or the alternate-scan order overtakes the address for reading according to the column direction order. In such a case, it is impossible to read all of the DCT processing results which have been written into the memory 103 according to the zigzag-scan order or the alternate-scan order. Thus, accurate decoding processing cannot be performed.
On the other hand, the method disclosed in Japanese Laid-Open Publication No. 10-334225 uses the double buffer formed by two buffers 203a and 203b each having a size capable of storing the processing result of the respective processing stages 202 and 204. In such a structure, the processing at the processing stage 202 and the processing at the processing stage 204 are continuously performed without interruption therebetween, whereby high speed processing is appropriately achieved. Moreover, all the processing results are read out, whereby accurate encoding/decoding is performed. However, it is necessary to provide two buffers 203a and 203b for respectively storing the processing results of the processing stages 202 and 204. Thus, the circuitry size cannot be reduced.
According to one aspect of the present invention, an image processing device includes: a DCT processing section which performs two-dimensional discrete cosine transform processing on digital image data; a quantization processing section for quantizing the image data which has undergone the two-dimensional DCT processing in the DCT processing section; a memory for storing the image data which has been quantized in the quantization processing section; a Huffman-encoding processing section for Huffman-encoding the image data read out from the memory to compress the image data; and an encoding control section which outputs a signal (DCTSTART) for beginning the processing of the DCT processing section, a signal (QSTART) for beginning the processing of the quantization processing section, and a signal (HUFFSTART) for beginning the processing of the Huffman-encoding processing section as well as a write control signal for writing the quantized image data into the memory and a read control signal for reading the image data from the memory for the Huffman-encoding processing, wherein the memory is a two-port memory which has a writing port and a reading port independent from each other and a capacity which can contain data for one block formed by Mxc3x97N pixels (where M and N are positive natural numbers, and Mxe2x89xa0Nxe2x88x921), and in the case where the data for one block is written into the memory according to a column direction order in response to the write control signal from the encoding control section, and the data for one block is read out from the memory according to a zigzag-scan order or an alternate-scan order in response to the read control signal from the encoding control section, a time difference between a time to start writing the data into the memory and a time to start reading the data from the memory is controlled by the write control signal and the read control signal such that all of the data written into the memory can be read out.
In one embodiment of the present invention, the memory can contain data for one block formed by 8xc3x978 pixels, i.e., M=N=8.
In another embodiment of the present invention, in the case where a delay between a time to start generating the result of the quantization processing in the quantization processing section and a time to start writing the generated result into the memory is xcex2 cycles, and a time difference between the start of writing of the result of the quantization processing and the end of reading of the result of the quantization processing is xcex1 cycles, xcex1 being set to a value which satisfies an expression:
28 less than xcex1 less than (36+xcex2), 
so that when a write cycle and a read cycle are equal, and a reading order is the zigzag-scan order, an address for writing never overtakes an address for reading.
In still another embodiment of the present invention, in the case where a delay between a time to start generating the result of the quantization processing in the quantization processing section and a time to start writing the generated result into the memory is xcex2 cycles, and a time difference between the start of writing of the result of the quantization processing and the end of reading of the result of the quantization processing is xcex1 cycles, xcex1 being set to a value which satisfies an expression:
10 less than xcex1 less than (58+xcex2), 
so that when a write cycle and a read cycle are equal, and a reading order is the alternate-scan order, an address for writing never overtakes an address for reading.
According to another aspect of the present invention, an image processing device includes: a Huffman-decoding processing section for Huffman-decoding a compressed image data; a memory for storing the image data which has undergone the Huffman-decoding processing in the Huffman-decoding processing section; an inverse quantization processing section for inversively quantizing the Huffman-decoded image data read out from the memory; an inverse DCT processing section which performs two-dimensional inverse DCT processing on the image data which has been inversively-quantized in the inverse quantization processing section; and a decoding control section which outputs a signal (IDCTSTART) for beginning processing of the inverse DCT processing section, a signal (IQSTART) for beginning processing of the inverse quantization processing section, and a signal (IHUFFSTART) for beginning processing of the Huffman-decoding processing section as well as a write control signal for writing the Huffman-decoded image data into the memory and a read control signal for reading the image data from the memory for the inverse quantization processing, wherein the memory is a two-port memory which has a writing port and a reading port independent from each other and a capacity which can contain data for one block formed by Mxc3x97N pixels (where M and N are positive natural numbers, and Mxe2x89xa0Nxe2x88x921), and in the case where the data for one block is written into the memory according to a zigzag-scan order or a alternate-scan order in response to the write control signal from the encoding control section, and the data for one block is read out from the memory according to a column direction order in response to the read control signal from the decoding control section, a time difference between a time to start writing the data into the memory and a time to start reading the data from the memory is controlled by the write control signal and the read control signal such that all of the data written into the memory can be read out.
In one embodiment of the present invention, the memory can contain data for one block formed by 8xc3x978 pixels, i.e., M=N=8.
In another embodiment of the present invention, in the case where a delay between a time to start generating the result of the Huffman-decoding processing and a time to start writing the generated result into the memory is xcex2 cycles, and a time difference between the start of writing of the result of the Huffman-decoding processing and the end of reading of the result of the Huffman-decoding processing is xcex1 cycles, xcex1 being set to a value which satisfies an expression:
28 less than xcex1 less than (36+xcex2), 
so that when a write cycle and a read cycle are equal, and a writing order is the zigzag-scan order, an address for writing never overtakes an address for reading.
In still another embodiment of the present invention, in the case where a delay between a time to start generating the result of the Huffman-decoding processing and a time to start writing the generated result into the memory is xcex2 cycles, and a time difference between the start of writing of the result of the Huffman-decoding processing and the end of reading of the result of the Huffman-decoding processing is xcex1 cycles, xcex1 being set to a value which satisfies an expression:
10 less than xcex1 less than (58+xcex2), 
so that when a write cycle and a read cycle are equal, and a writing order is the alternate-scan order, an address for writing never overtakes an address for reading.
According to still another aspect of the present invention, an image processing device includes: a DCT/inverse DCT processing section which is capable of performing both two-dimensional DCT processing on digital image data and two-dimensional inverse DCT processing on compressed image data and which is commonly utilized for the respective processings; a quantization/inverse quantization processing section which is capable of performing both quantization processing on the DCT-processed image data and inverse quantization processing on the inversively DCT-processed image data and which is commonly utilized for the respective processings; a Huffman-encoding/Huffman-decoding processing section which is capable of performing both Huffman-encoding processing on the quantized image data and Huffman-decoding processing on the inversively-quantized image data and which is commonly utilized for the respective processings; a two-port memory which has a writing port and a reading port independent from each other and a capacity which can contain data for one block formed by Mxc3x97N pixels (where M and N are positive natural numbers, and Mxe2x89xa0Nxe2x88x921); a selector for selecting data to be written into the two-port memory in response to a select signal which triggers encoding/decoding processing; and an encoding/decoding control section which outputs a processing start signal (DCTSTART or IDCTSTART) for the DCT/inverse DCT processing section, a processing start signal (QSTART or IQSTART) for the quantization/inverse quantization processing section, and a processing start signal (HUFFSTART or IHUFFSTART) for the Huffman-encoding/Huffman-decoding processing section as well as a write control signal and a read control signal to the two-port memory, wherein in the case where the select signal triggers encoding processing, the encoding/decoding control section sends a write control signal to the memory in order to write data for one block into the memory according to a column direction order and sends a read control signal to the memory in order to read data for one block from the memory according to a zigzag-scan order or an alternate-scan order; in the case where the select signal triggers decoding processing, the encoding/decoding control section sends a write control signal to the memory in order to write data for one block into the memory according to the zigzag-scan order or the alternate-scan order and sends a read control signal to the memory in order to read data for one block from the memory according to the column direction order; and in both of the encoding processing and the decoding processing, a time difference between a time to start writing the data into the memory and a time to start reading the data from the memory is controlled by the write control signal and the read control signal such that all of the data written into the memory can be read out.
In one embodiment of the present invention, the memory can contain data for one block formed by 8xc3x978 pixels, i.e., M=N=8.
In another embodiment of the present invention, in the case where a delay between a time to start generating the result of the Huffman-decoding processing and a time to start writing the generated result into the memory is xcex2cycles, and a time difference between the start of writing the result of the Huffman-decoding processing and the end of reading the result of the Huffman-decoding processing is xcex1 cycles, in encoding processing: when a write cycle and a read cycle are equal, and a reading order is the zigzag-scan order, xcex1 is set to a value which satisfies an expression,
28 less than xcex1 less than (36+xcex2), 
so that an address for writing never overtakes an address for reading; and when a write cycle and a read cycle are equal, and a reading order is the alternate-scan order, xcex1 is set to a value which satisfies an expression,
10 less than xcex1 less than (58+xcex2), 
so that an address for writing never overtakes an address for reading, and in decoding processing: when a write cycle and a read cycle are equal, and a writing order is the zigzag-scan order, xcex1 is set to a value which satisfies an expression,
28 less than xcex1 less than (36+xcex2), 
so that an address for writing never overtakes an address for reading; and when a write cycle and a read cycle are equal, and a writing order is the alternate-scan order, xcex1 is set to a value which satisfies an expression,
10 less than xcex1 less than (58+xcex2), 
so that an address for writing never overtakes an address for reading.
In an image processing device according to the present invention, in the case where coding (compression of images) is performed, a time difference between the time to start writing quantized data into a two-port memory having a capacity to store data for one block and having a writing port and a reading port independent from each other and the time to start reading the quantized data from the memory is controlled such that all of the quantized data for one block which has been written into the memory according to a column direction order can be read out according to a zigzag-scan order or an alternate-scan order. Thus, according to the present invention, even in a structure employing a single two-port memory, when DCT processing is continuously performed without interruption, it is possible to read all of the data from the memory by appropriately controlling the time difference between the start of writing and the end of reading.
In the case where decoding (decompression of images) is performed, a time difference between the time to start writing Huffman-decoded data for one block into a two-port memory having a capacity to store data for one block and having a writing port and a reading port independent from each other and the time to start reading the Huffman-decoded data for one block from the memory is controlled such that all of the Huffman-decoded data for one block which has been written into the memory according to a zigzag-scan order or an alternate-scan order can be read out according to a column direction order. Thus, according to the present invention, even in a structure employing a single two-port memory, when inverse DCT processing is continuously performed without interruption, it is possible to read all of the data from the memory by appropriately controlling the time difference between the start of writing and the end of reading.
The time difference between the start of writing data into a memory and the end of reading the data from the memory when the data is stored in the memory on the units of a block formed by 8xc3x978 pixels is described below.
Assume that the delay between the time to start the generation of data to be written into the memory and the time to start writing the generated data into the memory is xcex2 cycles, and the time difference between the start of writing and the end of reading is xcex1 cycles. In the case of coding (compression of images), when the write cycle and the read cycle are equal, and the reading order is a zigzag-scan order, the address for writing never overtakes the address for reading so long as xcex1 is set to a value which satisfies the following expression:
28 less than xcex1 less than (36+xcex2). 
When the write cycle and the read cycle are equal, and the reading order is an alternate-scan order, the address for writing never overtakes the address for reading so long as xcex1 is set to a value which satisfies the following expression:
10 less than xcex1 less than (58+xcex2). 
In the case of decoding (decompression of images), when the write cycle and the read cycle are equal, and the writing order is a zigzag-scan order, the address for writing never overtakes the address for reading so long as xcex1 is set to a value which satisfies the following expression:
28 less than xcex1 less than (36+xcex2). 
When the write cycle and the read cycle are equal, and the reading order is an alternate-scan order, the address for writing never overtakes the address for reading so long as xcex1 is set to a value which satisfies the following expression:
10 less than xcex1 less than (58+xcex2). 
Thus, the invention described herein makes possible the advantages of providing an image processing device: which can increase the processing speed of pipeline processing performed between discrete cosine transform processing/inverse discrete cosine transform processing and Huffman-encoding processing/Huffman-decoding processing for compression/expansion of color images; which achieves accurate encoding/decoding; and which decreases the size of the circuitry.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.